AD9523-1BCPZ

AD9523-1 is a low jitter clock generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS outputs. The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. It is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter clean-up to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. Application includes LTE and multicarrier GSM base stations, wireless and broadband infrastructure, medical instrumentation, clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, low jitter, low phase noise clock distribution, clock generation and translation for SONET, 10Ge, 10G FC, and other 10Gbps protocols, forward error correction (G.710), high performance wireless transceivers ATE and high performance instrumentation.

• Zero delay operation, dual VCO dividers
• Adjustable delay 63 resolution steps of ½ period of VCO output divider
• Duty cycle correction for odd divider settings
• Automatic synchronization of all outputs on power-up
• Non-volatile EEPROM stores configuration settings, dual PLL architecture
• Low bandwidth for reference input clock clean-up with external VCXO
• Phase detector rate up to 130MHz, redundant reference inputs
• Automatic and manual reference switchover modes, revertive and nonrevertive switching
• Low noise LVCMOS output from VCXO used for RF/IF synthesizers
• 72-lead LFCSP-VQ package, temperature range from -40°C to +85°C

Notes

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party