MC74VHC1GT125MU1TCG-Q

MC74VHC1GT125MU1TCG-Q is a single non-inverting 3-state buffer. The MC74VHC1G125 has CMOS−level input thresholds while the MC74VHC1GT125 has TTL−level input thresholds. The internal circuit is composed of three stages, including a buffered 3−state output which provides high noise immunity and stable output. The input structures provide protection when a voltage up to 5.5V is applied, regardless of the supply voltage. This allows the device to be used to interface 5V circuits to 3V circuits. Some output structures also provide protection when VCC = 0V and when the output voltage exceeds VCC. This input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc.

• AEC-Q100 qualified, positive DC supply voltage range from 2.0 to 5.5V
• Propagation delay is 4.5ns typ (25°C, 3.0 to 3.6V, CL=15pF)
• Inputs/outputs over voltage tolerant up to 5.5V, IOFF supports partial power down protection
• Source/sink 8mA at 3.0V, chip complexity <lt/> 100 FETs
• DC output voltage range from -0.5 to VCC + 0.5V (active−mode (high or low state))
• Input rise and fall time range from 0 to 20ns/V (VCC=2.0V)
• Quiescent supply current is 1µA max (25°C, VIN=VCC or GND, 5.5V)
• Input capacitance is 4pF typ (TA=25°C), output capacitance is 6pF typ (TA=25°C)
• Power dissipation capacitance is 8pF typ (25°C, VCC=5.0V)
• UDFN6 package, operating temperature range from -55 to +125°C